Indian Patent Application & Intellectual Property Disclosure Invention: Event-Gated Sparse Computation with Self-Calibrating Surprise Thresholds (Pulse Substrate & LPE Rule). Patent Office: Government of India — The Patents Act, 1970 & The Patents Rules, 2003 (Form 2 Provisional Specification). Inventor & Applicant: Er. Infant Nirmal Priyan J, Adrient Pvt Ltd, Bangalore, Karnataka, India. 1. Abstract & Architecture Overview Two fundamental costs dominate contemporary sequence modeling: the quadratic attention overhead over context length and the immense datacenter energy required for global backpropagation through time. Pulse introduces an event-driven recurrent substrate where computation is conditional on surprise: each dynamical unit updates its state only when input deviation from a learned running expectation exceeds a self-calibrating threshold. Crucially, the exact same local prediction-error signal that gates computation also drives all synaptic learning. There is no global backward pass, no computational gradient graph, and no inter-module synchronization anywhere in the substrate. 2. Core Mathematical Formulations Formula 1 — Event Gating Dynamics surprise_i(t) = || x_i(t) - EMA_i(x) ||₁ EMA_i ← (1 - β)·EMA_i + β·x_i(t) [β = 0.01] fire_i(t) = (surprise_i(t) > θ_i) A cell fires only when deviation from running expectation crosses threshold θ. Inactive cells consume zero computational operations. Formula 2 — State Persistence & Sparsity if fire: s_i(t) = tanh(W_in x_i(t) + Σ_j A_ij s_j(t-1) + b_i) else: s_i(t) = s_i(t-1) [Zero Compute] Unfired cells maintain their exact state without computing synaptic gathers, achieving 5× to 20× compute reductions on structured inputs. Formula 3 — Self-Calibrating Threshold Update θ_i ← θ_i + μ · ( |e_i(t)| - θ_i ) The threshold learns directly from local prediction error e_i. Compute gating, learning gating, and memory gating are unified in a single signal. Formula 4 — Local Prediction Error (LPE) Plasticity x̂_i(t+1) = P_i( s_i(t) ) + p0_i e_i(t) = x_i(t+1) - x̂_i(t+1) W_i ← W_i - η · e_i(t) · (∂x̂_i / ∂W_i) Every cell predicts its own next input. Weight updates depend strictly on local pre- and post-synaptic variables with closed-form analytical shrinkage. 3. Multiply-Free Ternary Execution for Commodity CPUs Following quantization-aware stabilization, substrate synaptic weights are constrained to the ternary set {-1, 0, +1}. Consequently, large-scale matrix-vector dot products transform into multiply-free addition and subtraction chains: dot_product(W_ternary, x) = sum(x[pos_indices]) - sum(x[neg_indices]) Maps directly to SIMD integer instructions (AVX2, AVX-512, and ARM NEON) without requiring tensor processing units (TPUs) or high-wattage GPUs. 4. Empirical Validation & Experimental Proof Evaluation Metric Empirical Result Baseline / Target Verification Reference Deterministic Reproducibility 100 / 100 bit-exact matches ≥ 99% reproducibility g4_wave0::t5b Gradient Match vs Finite Differences 10⁻¹⁵ relative error ≤ 10⁻⁸ numerical tolerance g4_wave1::t8_w_in_gradient Synaptic Drift Stability ||ΔW_in|| = 48.8, ||ΔA|| = 0.295 Strictly bounded plasticity G4 Dense Integration Event Compute Sparsity 5× to 20× FLOP reduction ≥ 3× reduction Pulse Native Engine
