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AETHERION — Continuous Neuromorphic Intelligence on Your Device

AETHERION is Adrient's on-device AI architecture: it learns continuously from streaming experience, remembers what matters, and tells you honestly how confident it is — running on ordinary CPUs without GPUs or cloud datacenters. Protected under Indian Patent Applications filed with the Government of India.

Govt of India Patent Filing Form 2 · The Patents Act, 1970 & Patent Rules, 2003

System and Method for Continuous Neuromorphic Deliberation Gating, Local Recurrent Attractor Discordance Resolution, and Asymmetric Harm Shielding

Applicant & Inventor: Er. Infant Nirmal Priyan J
Organization: Adrient Pvt Ltd (Bangalore, India)
Official Filing Date: September 18, 2026
Patent Invention 1

Pulse: Event-Gated Sparse Substrate

Cells fire only when input novelty crosses self-calibrating thresholds. All learning is driven by Local Prediction Error (LPE) without backpropagation.

Patent Invention 2

Aeon Core: On-Device Continual Memory

Surprise-gated episodic writes, importance-weighted decay, and calibrated Certainty Signals solve catastrophic forgetting on consumer CPUs.

Patent Invention 3

Deliberation & Asymmetric Harm Shield

Continuous top-2 margin gating (81.26% bypass) and strict shortlist constraints guarantee a 5.24 : 1 rescue-to-break ratio in sequence transitions.

Architectural Breakthrough

What Problems AETHERION Solves

Quadratic Attention & Compute Explosion

Attention cost scales quadratically with history length. AETHERION uses event-gated recurrence with O(1) step latency.

Datacenter Dependency & Cloud Latency

Runs natively on commodity CPUs (Intel, AMD, ARM, Apple Silicon). Operates 100% offline with zero cloud telemetry.

Session Amnesia & Catastrophic Forgetting

Aeon Core provides encrypted, continual memory with importance-weighted decay, achieving 100% concept retention.

Deliberation Harm & False Interventions

Patented Asymmetric Harm Shielding achieves a 5.24 : 1 rescue-to-break ratio, systematically guaranteeing that reasoning steps improve accuracy.

Mathematical Foundations

How It Computes — Four Core Mathematical Principles

Computation is event-driven: a unit only works when its input exceeds a learned surprise threshold. All learning happens locally without backward passes.

1. Event-Gated Sparsity & State Persistence
$$\text{surprise}_i(t) = \| x_i(t) - \text{EMA}_i(x) \|_1$$ $$s_i(t) = \begin{cases} \tanh(W_{\text{in}} x_i(t) + \sum_j A_{ij} s_j(t-1) + b_i) & \text{if } \text{surprise} > \theta_i \\ s_i(t-1) & \text{else (zero compute)} \end{cases}$$

Cells fire only when change exceeds running expectation. Unfired units maintain state with zero arithmetic operations.

2. Local Prediction Error (LPE) Plasticity
$$\hat{x}_i(t+1) = P_i(s_i(t)) + p_{0,i}, \quad e_i(t) = x_i(t+1) - \hat{x}_i(t+1)$$ $$\Delta W_i = -\eta \cdot e_i(t) \cdot \frac{\partial \hat{x}_i}{\partial W_i} \cdot \frac{1}{1 + \gamma \cdot \text{gain}}$$

Learning occurs locally in forward time without gradient backpropagation, autograd graphs, or cross-layer synchrony.

3. Importance-Weighted Continual Memory Decay
$$\text{retention}_i(t) = \exp\left( -\frac{\lambda \cdot t}{\alpha \cdot \text{surprise}_i + (1-\alpha) \cdot \text{recency}_i} \right)$$

Biological forgetting keeps lifetime user memory searchable in megabytes. Salient memories persist; background noise fades.

4. Logit Margin Deliberation & Harm Shield
$$\Delta_t = z_t[(1)] - z_t[(2)] \ge \tau_{\text{margin}} \implies \text{Bypass Deliberation (81.26\%)}$$ $$\text{Switch to } c^* \iff c^* \in \text{Top-}4(z_t) \land c^* \ne y_{\text{reflex}} \land D(c^*) \ge 0.50$$

Statutory invention in Indian Patent Form 2: rescues incorrect reflex decisions at a verified 5.24 : 1 rescue-to-break ratio.

Empirical Confirmation
5-Seed Confirmation Panel & Efficacy Proof

Evaluated on complex second-order sequences with 10,000 scored decisions.

5.24 : 1
Rescue-to-Break Ratio
81.26%
Margin Bypass Rate
p = 5.47e-62
McNemar Exact Test
Publications & Patents

Aetherion Research Papers & Specifications

In-depth technical papers, mathematical formulations, and experimental verification for on-device neural processing.

All Research Architecture Memory Reasoning